1. Technical Field
The present invention relates to a semiconductor memory device, and more particularly, to a direct sense amplifier that is implemented in a semiconductor memory device having a hierarchical input/output line architecture.
2. Description
Generally, DRAMs use shared sense amplifiers. However, in a DRAM having a shared sense amplifier, when one wordline is activated in a specific memory cell array block, data can be accessed only by the number of pairs of input/output lines included in sense amplifiers on either side of the specific memory cell array block, regardless of the number of memory cells connected to the wordline. Due to this, it is difficult to access a large amount of data at the same time. To solve this problem, as shown in FIG. 1, a hierarchical input/output line architecture, which includes pairs of local input/output lines LIO, /LIO and pairs of global input/output lines GIO, /GIO, has been suggested.
In the hierarchical input/output line architecture shown in FIG. 1, pairs of local input/output lines LIO/LIO are connected to pairs of global lines GIO, /GIO via switches SW that are controlled by a block information signal BLKx. Data of pairs of bitlines BL, /BL is sense-amplified by bitline sense amplifiers 11 through 14. Data of the sense-amplified pairs of bit lines BL, /BL is transmitted to pairs of local input/output lines LIO, /LIO via column select transistors CT when column select lines CSL are activated and data of pairs of local input/output lines LIO, /LIO is transmitted to pairs of global input/output lines GIO, /GIO via the switches SW. Data of pairs of global input/output lines GIO, /GIO is amplified by input/output line sense amplifiers 15 and 16. In such a hierarchical input/output line architecture, the number of data accessible when one wordline is activated can be increased by controlling the lengths of pairs of local input/output lines LIO, /LIO.
As a method of reducing read latency in a DRAM having a general sense amplifier architecture, direct sense amplifier architectures as shown in FIGS. 2A and 2B have been proposed. In the direct sense amplifier architecture shown in FIG. 2A, in a write operation, data of input/output lines IO, /IO is transmitted to pairs of bitlines BL, /BL via transistors T1 and T2. In a read operation, charge of pairs of input/output lines IO, /IO is discharged to ground VSS via transistors T3 and T5 and transistors T4 and T6. Here, conductance of the transistor T5 controlled by a voltage of a bitline BL is different from conductance of the transistor T6 controlled by a voltage of a complementary bitline /BL. Thus, the amount of discharge of an input/output line IO is different from the amount of discharge of a complementary input/output line /IO. As a result, a potential difference occurs between the input/output line IO and the complementary input/output line /IO.
In the direct sense amplifier architecture shown in FIG. 2B, in the write operation, data of input/output lines IO, /IO is delivered to a pair of bitlines BL, /BL via transistors T7 and T8. In the read operation, charge of a pair of input/output lines IO/IO is discharged to ground VSS via transistors T9, T11, and T13 and transistors T10, T12, and T14. Here, conductance of the transistor T13 controlled by a voltage of a bitline BL is different from conductance of the transistor T14 controlled by a voltage of a complementary bitline /BL. Thus, the amount of discharge of the input/output line IO is different from the amount of discharge of the complementary input/output line /IO. As a result, a potential difference occurs between the input/output line IO and the complementary input/output line /IO. However, in the direct sense amplifier architecture, since several additional transistors are required in sense amplifier areas of each of pairs of bit lines, the chip area increases. Also, since a write column select line WCSLi and a read column select line RCSLi are respectively required, the number of interconnection lines doubles.
Accordingly, it would be desirable to provide a semiconductor memory device having a hierarchical input/output architecture and a direct sense amplifier which is implemented in the hierarchical input/output line architecture without increasing the chip area and the number of interconnection lines.
According to an aspect of the present invention, there is provided a semiconductor memory device including a pair of write control switches and a direct sense amplifier. The pair of write control switches is connected between a pair of complementary local input/output lines and a pair of complementary global input/output lines, and connects the pair of complementary local input/output lines and the pair of complementary global input/output lines in response to a write control signal. The direct sense amplifier is connected to the pair of complementary local input/output lines and the pair of complementary global input/output lines. The direct sense amplifier generates a voltage difference, corresponding to a voltage difference between the pair of complementary local input/output lines, between the pair of complementary global input/output lines in response to a read control signal.
In this aspect, the direct sense amplifier includes first through fourth direct sense amplifier switches. The first direct sense amplifier switch has an end connected to one of the complementary global input/output lines and responds to the read control signal. The second direct sense amplifier switch has an end connected to the other end of the first direct sense amplifier switch and the other end connected to ground and responds to a signal on one of the complementary local input/output line. The third direct sense amplifier switch has an end connected to a second (complementary) line of the complementary global input/output lines and responds to the read control signal. The fourth direct sense amplifier switch has an end connected to the other end of the third direct sense amplifier switch and the other end connected to ground and responds to a signal of a second (complementary) line of the complementary local input/output lines. Beneficially, the first through fourth direct sense amplifier switches are NMOS transistors.
The write control signal is generated by a logical combination of an inverted read signal, representing a read operation, and a block select signal for a memory cell array block. The read control signal is generated by a logical combination of the read signal and the block select signal.
According to another aspect of the present invention, there is also provided a semiconductor memory device including a pair of write control switches which is connected between a pair of complementary local input/output lines and a pair of complementary global input/output lines and responds to a write control signal, and a direct sense amplifier which is connected to the pair of local input/output lines and the pair of global input/output lines and generates a voltage difference, corresponding to a voltage difference between the pair of complementary local input/output lines, between the pair of complementary global input/output lines in response to a read signal representing a read operation and a block select signal for a memory cell array block.
In this aspect, the direct sense amplifier includes first through sixth direct sense amplifier switches. The first direct sense amplifier switch has an end connected to one of the complementary global input/output lines and responds to the read signal. The second direct sense amplifier switch has an end connected to the other end of the first direct sense amplifier switch and responds to the block select signal. The third direct sense amplifier switch has an end connected to the other end of the second direct sense amplifier switch and the other end connected to ground and responds to a signal of the complementary local input/output line. The fourth direct sense amplifier switch has an end connected to a second (complementary) line of the complementary global input/output lines and responds to the read signal. The fifth direct sense amplifier switch has an end connected to the other end of the fourth direct sense amplifier switch and responds to the block select signal. The sixth direct sense amplifier switch has an end connected to the other end of the fifth direct sense amplifier switch and the other end connected to ground and responds to a signal of a second (complementary) line of the complementary local input/output lines. Beneficially, the first through sixth direct sense amplifier switches are NMOS transistors.
The write control signal is generated by a logical combination of an inverted read signal and the block select signal.
According to still another aspect of the present invention, there is also provided a semiconductor memory device including a pair of write control switches which is connected between the pair of complementary local input/output lines and the pair of complementary global input/output lines and responds to an inverted signal of a read signal representing a read operation and a block select signal for a memory cell array block, and a direct sense amplifier which is connected to the pair of complementary local input/output lines and the pair of global input/output lines and generates a voltage difference, corresponding to a voltage difference between the pair of complementary local input/output lines, between the pair of complementary global input/output lines in response to the read signal and the block select signal.
In this aspect, the direct sense amplifier includes first through sixth direct sense amplifier switches. The first direct sense amplifier switch has an end connected to one of the complementary global input/output lines and responds to the read signal. The second direct sense amplifier switch has an end connected to the other end of the first direct sense amplifier switch and responds to the block select signal. The third direct sense amplifier switch has an end connected to the other end of the second direct sense amplifier switch and the other end connected to ground and responds to a signal of one of the complementary local input/output lines. The fourth direct sense amplifier switch has an end connected to a second (complementary) line of the complementary global input/output lines and responds to the read signal. The fifth direct sense amplifier switch has an end connected to the other end of the fourth direct sense amplifier switch and responds to the block select signal. The sixth direct sense amplifier switch has an end connected to the other end of the fifth direct sense amplifier switch and the other end connected to the ground and responds to a signal of a second (complementary) line of the complementary local input/output lines. Beneficially, the first through sixth direct sense amplifier switches are NMOS transistors.
The pair of write control switches includes a first switching device which has an end connected to one of the pair of complementary local input/output lines and responds to the block select signal, and a second switching device which has an end connected to the other end of the first switching device and the other end connected one of the pair of complementary global input/output lines and responds to the inverted signal of the read signal. Beneficially, the first and second switching devices are NMOS transistors.
According to a further aspect of the present invention, there is provided a semiconductor memory device including a pair of write control switches which is connected between a pair of complementary local input/output lines and a pair of complementary global input/output lines and responds to an inverted read signal, representing a read operation, and a block select signal for a memory cell array block, and a direct sense amplifier which is connected to the pair of complementary local input/output lines and the pair of complementary global input/output lines and generates a voltage difference, corresponding to a voltage difference between the pair of complementary local input/output lines, between the pair of complementary global input/output lines in response to a read control signal.
In this aspect, the direct sense amplifier includes first through fourth direct sense amplifier switches. The first direct sense amplifier switch has an end connected to one of the complementary global input/output lines and responds to the read control signal. The second direct sense amplifier switch has an end connected to the other end of the first direct sense amplifier switch and the other end connected to ground and responds to a signal of the complementary local input/output line. The third direct sense amplifier switch has an end connected to a second (complementary) line of the complementary global input/output lines and responds to the read control signal. The fourth direct sense amplifier switch has an end connected to the other end of the third direct sense amplifier switch and the other end connected to ground and responds to a signal on a second (complementary) line of the complementary local input/output lines.
The read control signal is generated by a logical combination of the read signal and the block select signal.
The pair of write control switches includes a first switching device which has an end connected to one of the pair of complementary local input/output lines and responds to the block select signal, and a second switching device which has an end connected to the other end of the first switching device and the other end connected one of the pair of complementary global input/output lines and responds to the inverted signal of the read signal. Beneficially, the first and second switching devices are NMOS transistors.